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features ? fully integrated low if receiver fully integrated gfsk modulator for 72, 144, 288, 576 and 1152 kbits/s high sensitivity of typically ?93 dbm due to integrated lna high output power of typically +4 dbm multi-channel operation ? 95 channels ? support frequency hopping (etsi) and digital modulation (fcc) supply-voltage range 2.9v to 3.6v (unregulated) auxiliary voltage regulator on chip (3.2v to 4.6v) low current consumption few low-cost external components integrated ramp-signal generator and power control for an additional power amplifier low profile lead-free plastic package qfn32 (5 mm 5 mm 0.9 mm) rohs compliant applications high-tech multi-user toys wireless game controllers telemetry wireless audio/video electronic point of sales wireless head set fcc cfr47, part 15, etsi en 300 328, en 300 440 and arib std-t- 66 compliant radio links 1. description the atr2406 is a single chip rf transceiver intended for applications in the 2.4-ghz ism band. the qfn32-packaged ic is a comp lete transceiver including image rejec- tion mixer, low if filter, fm demodulator, rssi, tx preamplifier, power-ramping generator for external power amplifier, integrated synthesizer, and a fully integrated vco and tx filter. no mechanical adjustment is necessary in production. the rf transceiver offers a clock recovery function on-chip. low-if 2.4-ghz ism transceiver atr2406 4779l?ism?09/06
2 4779l?ism?09/06 atr2406 figure 1-1. block diagram 2. pin configuration figure 2-1. pinning qfn32 - 5 5 lna ir-mixer vco reg reg_dec ramp_out tx_out rx_in vreg_vco reg_ctrl vs_reg vs_syn vreg iref cp ref_clk tx_data vtune aux reg aux reg test2 pu_reg pu_trx rx_on tx_on nole clock data enable limiter rssi demod bp ramp gen pll gaussian filter pa ctrl logic bus vco vs_ifd rx_data rssi vs_ifa vs_rx/t x test1 divider by 2 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 atr2406 pu_reg ref_clk rssi vs_ifd vs_ifa rx-clock ic iref rx_on ramp_out tx_out rx_in1 rx_in2 vs_trx enable data clock tx_data rx_data pu_trx nole tx_on reg_ctrl vreg vs_reg reg_dec v reg_vco vtune cp vs_syn ic ic
3 4779l?ism?09/06 atr2406 table 2-1. pin description pin symbol function 1 pu_reg power-up input for auxiliary regulator 2 ref_clk reference frequency input 3 rssi received signal strength indicator output 4 vs_ifd digital supply voltage 5 vs_ifa analog supply voltage for if circuits 6 rx-clock rx-clock, if rx mode with clock recovery is active 7 ic internally connected. connect to v s if internal aux regulator is not used 8 iref external resistor for band-gap reference 9 reg_ctrl auxiliary voltage regulator control output 10 vreg auxiliary voltage regulator output 11 vs_reg auxiliary voltage regulator supply voltage 12 reg_dec decoupling pin for vco_reg 13 vreg_vco vco voltage regulator 14 vtune vco tuning voltage input 15 cp charge-pump output 16 vs_syn synchronous supply voltage 17 vs_trx transmitter receiver supply voltage 18 rx_in2 differential receiver input 2 19 rx_in1 differential receiver input 1 20 tx_out tx driver amplifier output 21 ramp_out ramp generator output for pa power ramping 22 ic internally connected, do not connect on pcb 23 ic internally connected, do not connect on pcb 24 rx_on rx control input 25 tx_on tx control input 26 nole open loop enable input 27 pu_trx rx/tx/pll/vco power-up input 28 rx_data rx data output 29 tx_data tx data input 30 clock 3-wire-bus: clock input 31 data 3-wire-bus: data input 32 enable 3-wire-bus: enable input paddle gnd ground
4 4779l?ism?09/06 atr2406 3. functional description 3.1 receiver the rf signal at rf_in is differentially fed through the lna to the image rejection mixer ir_mixer, driving the integrated low-if band-pass filter. the if frequency is 864 khz. the limiting if_amp with an integrated rssi functi on feeds the signal to the digital demodulator demod. no tuning is required. data slicing is hand led internally. 3.2 clock recovery for a 1152-kbit/s data rate, the receiver has a clock recovery function on-chip. the receiver includes a clock re covery circuit which regenerates the clock out of the received data. the advantage is that this recovered clock is synchronous to the clock of the transmitting device (and thus to the transmitted data), which significantly reduces the load of the process- ing microcontroller. the falling edge of the clock is the optimal sampling position for the rx_data signal, so at this event the data must be sampled by the microcontroller. the recovered clock is available at pin 6. 3.3 transmitter the transmit data at tx_data is filtered by an integrated gaussian filter (gf) and fed to the fully integrated vco operating at twice the output frequency. after modulation, the signal is frequency divided by 2 and fed to the internal preamplifier pa. this preamplifier supplies typi- cally +4 dbm output power at tx_out. a ramp-signal generator ramp_gen, providing a ramp signal at ramp_out for the external power amplifier, is integrated. the slope of the ramp signal is controlled internally so that spu- rious requirements are fulfilled. 3.4 synthesizer the ir_mixer, the pa, and the programmable counter (pc) are driven by the fully integrated vco, using on-chip inductors and varactors. the output signal is frequen cy divided to supply the desired frequency to the tx_driver, the 0/90 degree phase shifter for the ir_mixer, and to be used by the pc for the phase detector (pd) (f pd = 1.728 mhz). open loop modula- tion is supported. 3.5 power supply an integrated band-gap?stabilized voltage regulator for use with an external low-cost pnp transistor is implemented. multiple power-down and current saving modes are provided.
5 4779l?ism?09/06 atr2406 electrostatic sensitive device. observe precautions for handling. 4. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . parameters symbol min. max. unit supply voltage auxiliary regulator v s ?0.3 +4.7 v supply voltage v s ?0.3 +3.6 v control voltages v contr ?0.3 v s v storage temperature t stg ?40 +125 c input rf level p rf +10 dbm esd protection v esd_ana tbd v v esd_dig tbd v 5. operating range parameters symbol min. max. unit supply voltage v s 2.9 3.6 v auxiliary regulator supply voltage v s_batt 3.2 4.6 v temperature ambient t amb ?10 +60 c input frequency range f rx 2400 2483 mhz
6 4779l?ism?09/06 atr2406 6. electrical characteristics v s = 3.6v with aux regulator, t amb = 25c, unless otherwise specified no. parameters test conditions symbol min. typ. max. unit 1 supply 1.1 supply voltage with aux regulator v s 3.2 3.6 4.6 v 1.2 supply voltage without aux regulator v s 2.9 3.0 3.6 v 1.3 rx supply current cw mode (peak current) i s 57 ma burst mode at 10 kbits/s (4) i s 625 a 1.4 tx supply current cw mode (peak current) i s 42 ma burst mode at 10 kbits/s (4) i s 500 a 1.5 battery lifetime of a remote control application using an avr ? see section 10. ?appendix: current calculations for a remote control? on page 20 1.6 supply current in power-down mode with aux regulator pu_trx = 0; pu_reg = 0 i s < 1 a 1.7 supply current in power-down mode without aux regulator pu_trx = 0; pu_reg = 0 i s < 1 a 2 voltage regulator 2.1 aux regulator vreg 3.0 v 2.2 vco regulator vreg_vco 2.7 v 3 transmitter part 3.1 tx data rate 72/144/288/576/1152 kbits/s 3.2 output power ptx 4 dbm 3.3 tx data filter clock 9 taps in filter f txfclk 10.368/13.824 mhz 3.4 frequency deviation to be tuned by gfcs bits gf fm_nom 400 khz 3.5 frequency deviation scaling (3) gffm = gf fm_nom gfcs (refer to bus protocol d9 to d11) gfcs 60 130 % 3.6 frequency drift with standard loop filter and slot length of 1400 s (refer to the application note ?atr2406 loop filter and data rates?) ? fo (drift) 40 khz 3.7 harmonics bw = 100 khz (1) ?41.2 dbm 3.8 spurious emissions 30 ? 1000 mhz 1 ? 12.75 ghz 1.8 ? 1.9 ghz 5.15 ? 5.3 ghz bw = 100 khz (1) ?57 ?57 ?57 ?57 dbm dbm dbm dbm 4 ramp generator, pin 21 4.1 minimum output voltage tx_on = low v min 0.7 v 4.2 maximum output voltage refer to bus protocol d12 to d13 v max 1.1 1.9 v 4.3 rise time t r 5s 4.4 fall time t f 5s notes: 1. measured and guaranteed only on the atmel ? evaluation board, including microstr ip filter, balun, and smart radio fre- quency (smart rf) firmware. conducted measured. 2. timing is determined by external loop filter characteristics. faster timing can be achieved by modification of the loop filte r. for further information refer to the application notes. 3. the gaussian filter control setting (gfcs) is used to co mpensate production tolerances by tuning the modulation deviation in production to the nominal value of 400 khz. 4. burst mode with 0.9% duty cycle
7 4779l?ism?09/06 atr2406 5 receiver part 5.1 rx input impedance differential z in 170 + j0 ? 5.2 sensitivity at input for ber 10 -3 at 1152 kbits/s (1) ?93 dbm 5.3 third order input intercept point iip3 ?15 dbm 5.4 intermodulation rejection ber < 10 -3 , wanted at -83 dbm, level of interferers in channels n + 2 and n + 4 (1) im 3 32 dbc 5.5 co-channel rejection ber < 10 -3 , wanted at ?76 dbm (1) r co ?11 dbc 5.6 adjacent channel rejection 1.728 mhz ber < 10 -3 , wanted at ?76 dbm, adjacent level referred to wanted channel level (1) r i (n ? 1) 14 dbc 5.7 bi-adjacent channel rejection 3.456 mhz ber < 10 -3 , wanted at ?76 dbm, bi-adjacent level referred to wanted channel level (1) r i (n ? 2) 30 dbc 5.8 rejection with 3 channels separation 5.128 mhz ber < 10 -3 , wanted at ?76 dbm, n 3 adjacent level referred to wanted channel level (1) r i (n 3) 40 dbc 5.9 out of band rejection > 6 mhz ber < 10 -3 , wanted at ?83 dbm at 2.45 ghz (1) bl df>6mhz 38 dbc 5.10 out of band rejection 2300 mhz to 2394 mhz 2506 mhz to 2600 ghz ber < 10 -3 , wanted at ?83 dbm at 2.45 ghz (1) bl near 47 dbc 5.11 out of band rejection 30 mhz to 2300 mhz 2600 mhz to 6 ghz ber < 10 -3 , wanted at ?83 dbm at 2.45 ghz (1) bl far 57 dbc 6 rssi part 6.1 maximum rssi output voltage under high rx input signal level v rssimax 2.1 v 6.2 rssi output voltage, monotonic over range ?96 dbm to ?36 dbm with ?33 dbm at rf input with ?96 dbm at rf input v rssi 1.9 0.1 v v 7vco 7.1 oscillator frequency defined at tx output over full temperature range (1) 2400 2483 mhz 7.2 frequency control voltage range v vtune 0.5 v cc ? 0.5 v 7.3 vco tuning input gain defined at tx output g vco 240 mhz/v 6. electrical characteristics (continued) v s = 3.6v with aux regulator, t amb = 25c, unless otherwise specified no. parameters test conditions symbol min. typ. max. unit notes: 1. measured and guaranteed only on the atmel ? evaluation board, including microstr ip filter, balun, and smart radio fre- quency (smart rf) firmware. conducted measured. 2. timing is determined by external loop filter characteristics. faster timing can be achieved by modification of the loop filte r. for further information refer to the application notes. 3. the gaussian filter control setting (gfcs) is used to co mpensate production tolerances by tuning the modulation deviation in production to the nominal value of 400 khz. 4. burst mode with 0.9% duty cycle
8 4779l?ism?09/06 atr2406 8 synthesizer 8.1 external reference input frequency d7 = 0 d7 = 1 ref_clk 10.368 13.824 mhz mhz 8.2 sinusoidal input signal level (peak-to-peak value) ac-coupled sine wave ref_clk 500 1000 mv pp 8.3 scaling factor prescaler s psc 32/33 - 8.4 scaling factor main counter s mc 86/87/88/89 - 8.5 scaling factor swallow counter s sc 031- 9 phase detector 9.1 phase detector comparison frequency f pd 1728 khz 10 charge-pump output 10.1 charge-pump output current v cp = 1/2 v cc i cp 2 ma 10.2 leakage current v cp = 1/2 v cc i l 100 1000 pa 11 timing conditions (1)(2) 11.1 transmit to receive time reference clock stable tx rx time 200 s 11.2 receive to transmit time reference clock stable rx tx time 200 s 11.3 channel switch time reference clock stable cs time 200 s 11.4 power down to transmit reference clock stable pd tr time 250 s 11.5 power down to receive reference clock stable pd rx time 200 s 11.6 programming register reference clock stable prr time 3 s 11.7 pll settling time reference clock stable pll set time 200 s 12 interface logic in put and output signal level s, pin data, clock, enable 12.1 high-level input voltage logic 1 v ih 1.4 3.1 v 12.2 low-level input voltage logic 0 v il ?0.3 +0.4 v 12.3 high-level out put voltage logic 1 v oh 3.1 v 12.4 low-level output voltage logic 0 v ol 0v 12.5 input bias current logic 1 or logic 0 i bias ?5 +5 a 12.6 3-wire bus clock frequency f clkmax 10 mhz 6. electrical characteristics (continued) v s = 3.6v with aux regulator, t amb = 25c, unless otherwise specified no. parameters test conditions symbol min. typ. max. unit notes: 1. measured and guaranteed only on the atmel ? evaluation board, including microstr ip filter, balun, and smart radio fre- quency (smart rf) firmware. conducted measured. 2. timing is determined by external loop filter characteristics. faster timing can be achieved by modification of the loop filte r. for further information refer to the application notes. 3. the gaussian filter control setting (gfcs) is used to co mpensate production tolerances by tuning the modulation deviation in production to the nominal value of 400 khz. 4. burst mode with 0.9% duty cycle
9 4779l?ism?09/06 atr2406 7. pll principle figure 7-1. pll principle programable counter pc "- main counter mc "- swallow counter sc f vco = 1728 khz (s mc 32 + s sc ) phase frequency divider by 2 pa driver detector pd vco mixer f pd = 1728 khz gaussian filter gf reference counter rc ref_clk d7 13.824 mhz 1 pll reference txdat frequency ref_clk baseband controller 0 10.368 mhz external loop filter charge pump
10 4779l?ism?09/06 atr2406 table 7-1 shows the lo frequencies for rx and tx in the 2.4-ghz ism band. there are 95 channels available. since the atr2406 s upports wideband modulation with 400-khz devia- tion, every second channel can be used without overlap in the spectrum. 7.1 tx register setting the following 16-bit word ha s to be programmed for tx. note: d12 and d13 are only relevant if ramping generator in conj unction with external pa is used, otherwise it can be programmed 0 or 1. the vramp voltage is used to control the output power of an external power amplifier. the voltage ramp is started with the tx_on signal. these bits are only relevant in tx mode. table 7-1. lo frequencies mode f if /khz channel f ant /mhz f vco / mhz divided by 2 s mc s sc n tx c0 2401.056 2401.056 86 27 2779 c1 2401.920 2401.920 86 28 2780 ... ... ... ... ... ... c93 2481.408 2481.408 89 24 2872 c94 2482.272 2482.272 89 25 2873 rx 864 c0 2401.056 2401.920 86 28 2780 c1 2401.920 2402.784 86 29 2781 ... ... ... ... ... ... c93 2481.408 2482.272 89 25 2873 c94 2482.272 2483.136 89 26 2874 msb lsb data bits d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 01 pa gfcs 1rc mc sc table 7-2. output power settings with bits d12 - d13 pa (output power settings) d13 d12 ramp_out (pin 21) 0 0 1.3v 0 1 1.35v 1 0 1.4v 1 1 1.75v
11 4779l?ism?09/06 atr2406 7.2 rx register setting there are two rx settings possible. for a data rate of 1152 kbits/s, an internal clock recovery function is implemented. 7.3 register setting wi thout clock recovery must be used for data rates below 1.152 mbits/s. note: x values are not relevant and can be set to 0 or 1. 7.4 rx register setting with internal clock recovery recommended for 1.152-mbit/s data rate. the output pin of the recovered clock is pin 6. the falling edge of the recovered clock signal samples the data signal. note: x values are not relevant and can be set to 0 or 1. 7.5 pll settings rc, mc and sc bits control the synthesizer frequency as shown in table 7-3 , table 7-4 on page 12 and table 7-5 on page 12 . formula for calculating the frequency: tx frequency: f ant = 864 khz (32 s mc + s sc ) rx frequency: f ant = 864 khz (32 s mc + s sc ? 1) msb lsb data bits d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 1xxxxx0rc mc sc msb data bits d24 d23 d22 d21 d20 d19 d18 d17 d16 10100 0000 lsb data bits d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0xxx xx0rc mc sc table 7-3. pll settings of the reference counter bit d7 rc (reference counter) d7 clk reference 0 10.368 mhz 1 13.824 mhz
12 4779l?ism?09/06 atr2406 7.6 gfcs adjustment the gaussian filter control setting (gfcs) is used to compensate for production tolerances by tuning the modulation deviation in production to the nominal value of 400 khz. these bits are only relevant in tx mode. table 7-4. pll settings of the main counter bits d5 to d6 mc (main counter) d6 d5 s mc 0086 0187 1088 1189 table 7-5. pll settings of the swallo w counter bits d0 to d4 sc (swallow counter) d4 d3 d2 d1 d0 s sc 000000 000011 000102 ... ... ... ... ... ... 1110129 1111030 1111131 table 7-6. gfcs adjustment of bits d9 - d11 gfcs d11 d10 d9 gfcs 0 0 0 60% 0 0 1 70% 0 1 0 80% 0 1 1 90% 10 0100% 10 1110% 11 0120% 11 1130%
13 4779l?ism?09/06 atr2406 7.7 control signals the various transceiver functions are activated by the following control signals. a timing pro- posal is shown in figure 7-3 on page 14 7.8 serial programming bus the transceiver is programmed by the spi (clock, data and enable). after setting the enable signal to low, the data is transferred bit by bit into the shift register on the rising edge of the clock signal, starti ng with the msbit. when the enable signal has returned to high, the programmed information is active. additional leading bits are ignored and there is no check made of how many clock pulses arrived during enable low. the programming of the transceiver is done by a 16-bit or 25-bit data word (for the rx clock recovery mode). 7.9 3-wire bus timing figure 7-2. 3-wire bus protocol timing diagram table 7-7. control signals and functions signal functions pu_reg activates aux voltage regulator and the vco voltage regulator supplying the complete transceiver pu_trx activates rx/tx blocks rx_on activates rx circuits: demod, if amp, ir mixer tx_on activates tx circuits: pa, ramp gen, starts ramp signal at ramp_out nole disables open loop mode of the pll data clock enable tt tec ts tc th tl tper table 7-8. 3-wire bus protocol table description symbol minimum value unit clock period tper 100 ns set time data to clock ts 20 ns hold time data to clock th 20 ns clock pulse width tc 60 ns set time enable to clock tl 100 ns hold time enable to data tec 0 ns time between two protocols tt 250 ns
14 4779l?ism?09/06 atr2406 figure 7-3. example tx and rx timing diagram data 16/25 bits 16 bits ref_clk ref_clk data pin name mode c1 c5 c3 c2 c1 c4 c3 c2 c1 power-down power-up programming active rx-slot power-down optional power-up optional programming active tx-slot power-down > 40 s > 200 s > 50 s valid signal > 200 s > 40 s > 50 s vs 0 v 0 v vs pu_reg pin 1 pu_trx pin 27 tx_data pin 29 3w_clk pin 30 3w_data pin 31 3w_ena pin 32 nole pin 26 ref_clk pin 2 rx_on pin 24 tx_on pin 25 rx_data pin 28 rssi pin 3 ramp_out pin 21 connected to ramp_in of optional pa signals from trx (output) signals to trx (input) preamble (1-0-1-0) note: 1. keep input signals on low level during power-down state of trx
15 4779l?ism?09/06 atr2406 7.10 received signal st rength indication (rssi) the rssi is given as an analog voltage at the rssi pin. a typical plot of the rssi value is shown in figure 7-4 . figure 7-4. typical rssi value versus input power table 7-9. description of the conditions/states condition description c1 power down atr2406 is switched off and the supply current is lower than 1 a. c2 power up atr2406 is powered up by toggling pu_reg and pu_trx to high. pu_reg enables the external aux regulator transistor including vco regulator. pu_trx enables internal blocks like the pll and the vco. depending on the value of the external capacitors (for example, at the aux regulator, if one is used), it is necessary to wait at least 40 s until the different supply voltages have settled. c3 programming the internal register of the atr2406 is programmed via the three-wire interface. at tx, this is just the pll (transmit c hannel) and the deviation (gaussian filter). at rx, this is just the pll (receive channel) and, if the clock recovery is used, also the bits to enable this option. at the start of the three-wire programming, the enable signal is toggled from high to low to enable clocking the data into the internal register. when the enable signal rises again to high, the programmed data is latched. this is the time point at which the settling of the pll starts. it is necessary to wait the settling time of 200 s so that the vco frequency is stable. the reference clock needs to be applied to atr2406 for at least the time when the pll is in operation, which is the pr ogramming state (c3) and the active slot (c4, c5). out of the reference clock, several internal signals are also derived, for example, the gaussian filter circuitry and tx_data sampling. c4 this is the receive slot where the transmit burst is received and data as well as recovered clock are available. c5 this is the active transmit slot. as soon as tx_data is applied to atr2406, the signal nole toggles to low which enables modulation in open-loop mode. the preamble (1-0-1-0 pattern) should st art being sent at the start of tx_on. 0.0 0.5 1.0 1.5 2.0 2.5 -130 -110 -90 -70 -50 -30 -10 10 rf level (dbm) rssi level (v)
16 4779l?ism?09/06 atr2406 8. application circuit the atr2406 requires only a few low-cost external components for operation. a typical appli- cation is shown in figure 8-3 on page 17 . 8.1 typical application circuit figure 8-1. microcontroller interfacing with gene ral purpose mcu, pin connections between microcontroller and atr2406 figure 8-2. example with avr mcu note: 1. xtal: for example, xrfbcc-nanl; 13.824 mhz, 10 ppm order at: taitien electronic, taitien specific no.: a009-x-b26-3, smd microcontroller atr2406 configuration and control rf-data interface tx_data rx_data rx-clock data clock enable ctrl_lines xtal_out ref_clk xtal (1) atr2406 rf_ctrl rf_data avr_mcu usart gpio r 13.824 mhz xtal ref_clk nole enable clock data tx_on rx_on pu_trx pu_reg gpio1 gpio2 txd rxd xck gpio3 gpio4 gpio5 tx_data rx_data rx-clock rssi
17 4779l?ism?09/06 atr2406 figure 8-3. application circuit for atr2406-dev-board pu_reg ref_clk rssi vs_ifd vs_ifa rx-clock ic iref enable data clock tx_data rx_data pu_trx nole tx_on rx_on ic ic ramp_out tx_out rx_in1 rx_in2 vs_trx reg_ctrl vreg vs_reg reg_dec vreg_vco vtune cp gnd 32 31 30 29 28 27 26 25 enable data clock tx_data rx_data pu_trx nole tx_on pu_reg ref_clk rssi 1 2 3 c11 18p 4 5 6 7 c24 4p7 r3 62k 8 c16 47 c15 100n c23 4n7 9 10 c12 100n c13 47 bc808 t1 v s j2 11 12 c17 nc c19 c18 68p 470n 13 14 c21 2n2 15 16 g vs_syn 17 c14 nc c20 22n r4 1k0 18 19 c10 1p8 strip-balun rx_on 24 23 22 21 tp1 tp2 20 c9 1p5 strip vbatt strip c1 5p6 ic2 atr2406 ic2p gnd slug gnd2 gnd7 gnd8 gnd9 gnd4 gnd5 gnd6 gnd1 gnd3 rx-clock c4 390p c20, c21, cog dielectric ramp_out ramp j26 strip lowpassfilter c6 2p2 c7 2p2 c3 1p8 rfout (ant) j24 select integrated f-antenna or sma connector by setting the 0r resistor nc r2 ant2 ant gnd gnd r1 nc ant f-antenna j2 smasi j1 j4 vbatt 1 3 5 7 2 4 6 8 j11 vbatt 10 j5 j6 j7 tx_on tx_data pu_trx 12 14 16 j12 j13 j14 j15 j16 j17 enable data nole pu_reg rx-clock rx_data 9 11 13 j8 clock 15 j9 rx_on 17 18 20 22 24 26 28 j18 j19 j20 j21 vlsi connector 19 21 23 25 27 j10 rssi j3 ref_clk 1k5 r5 r6 1k5
18 4779l?ism?09/06 atr2406 9. pcb layout design figure 9-1. pcb layout atr2406-dev-board
19 4779l?ism?09/06 atr2406 table 9-1. bill of materials part value part number vendor package comment c1 5.6 pf gjm1555c1h5r6cb01 or grm1555c1h5r6dz01 murata ? 0402 c3, c10 1.8 pf gjm1555c1h1r8cb01 or grm1555c1h1r8cz01 murata 0402 c4 390 pf grm1555c1h391ja01 murata 0402 c5 4.7 pf gjm1555c1h4r7cb01 or grm1555c1h4r7cz01 murata 0402 nc c6, c7 2.2 pf gjm1555c1h2r2cb01 or grm1555c1h2r2cz01 murata 0402 c9 1.5 pf gjm1555c1h1r5cb01 or grm1555c1h1r5cz01 murata 0402 c11 18 pf grm1555c1h180jz01b murata 0402 c12, c15 100 nf grm155r71c104ka88b murata 0402 c13, c16 4.7 f b45196h2475m109 epcos ? 3216 optional (2) c14 1 nf grm15r71h102kb01 murata 0402 nc c17 3.3 nf grm15r71h332kb01 murata 0402 nc c18 68 pf grm1555c1h680jz01b murata 0402 c19 470 nf grm18f51h474zb01 (0402) or grm188r61a474ka61b (0603) murata 0402/0603 c20 22 nf, cog grm21b5c1h223ja01 murata 0805 cog, important for good rf performance c21 2.2 nf, cog grm1885c1h222ja01 murata 0603 cog, important for good rf performance c23 4.7 nf grm155r71h472ka01b murata 0402 c24 4.7 pf grm1555c1h4r7cz01b murata 0402 l6 8.2 nh we-mk0402 744784082 wrth ? electronic 0402 nc, microstrip used r3 62 k ? 62k, 5% vishay ? 0402 r4 1.0 k ? 1k0, 5% vishay 0402 r5 1.5 k ? 1k5, 5% vishay 0402 ref_clk level, optional (1) r6 1.5 k ? 1k5, 5% vishay 0402 ref_clk level, optional (1) ic2 atr2406 atr2406 atmel mlf32 t1 bc808-40 bc808-40, any standard type can be used, but it is important that be ??40?! vishay, philips ? , etc. sot-23 optional (2) msub fr4 fr4, e_r = 4.4 at 2.45 ghz, h = 500 m, t = 35 m, t and = 0.02, surface, that is, chem. tin or chem. gold notes: 1. not necessary if supplied refclk level is within specification range 2. if no aux regulator is used, then t1 and c16 can be removed and a jumper is needed from the collector to the emitter pad. additionally, pin 7 of the atr2406 has to be connected to pin 4 or pin 5 to use the integrat ed f antenna, set jumper r2 (0r resistor 0603) table 9-2. parts count bill of materials parts count required (minimal bom) optional (depending on application) capacitors 0402 14 14 capacitors >0402 2 4 resistors 0402 2 2 inductors 0402 ? ? semiconductors 1 2
20 4779l?ism?09/06 atr2406 10. appendix: current calculations for a remote control assumptions: basic numbers: amount of current needed to transmit one packet: protocol a data packet consists of 24 bytes. 24 bytes = 240 bits (usart connection) t packet_length = 210 s at 1.152 mbits/s channel the system will use five predefined channels for frequency hopping spread spectrum (fhss) which gives improved immunity against interferers loop filter loop filter settling time will be 110 s handheld device if not in use, the handheld device will be in power-down mode with the avr?s watchdog timer disabled. the avr power-down current is typically 1.25 a. if an external voltage regulator is used, additional power-down current has to be taken into account base station device the base station will periodically scan all the channels of the used subset. the base station will stay on one channel for 2 seconds. if the base station receives a correct packet, an acknowledge will be returned to the handheld device. the power consumption of the base station device is not power-sensitive, as this part of the application is normally mains powered peak current atr2406 in tx at 1.152 kbits/s 42 ma peak current atr2406 in rx at 1.152 kbits/s 57 ma peak current atr2406 with synthesizer running 26 ma current atmega88 active 5 ma current atmega88 power down (no wdt) 1.25 a current atmega88 power down (+ wdt) 5 a loop settling time of atr2406 110 s configuration of atr2406 30 s time needed for exchanging a packet at 1.152 kbits/s 210 s q1 = (0.005a + 0.026a) 5030 s = 155 as (charge up time atr2406 + avr internal calculations) q2 = (0.005a + 0.026a) 30 s = 0.93 as (charge for configuring the atr2406) q3 = (0.005a + 0.026a) 110 s = 3.41 as (charge for settling the loop filter) q4 = (0.005a + 0.042a) 210 s = 9.87 as (charge for transmitting the packet) q5 = (0.005a) 250 s = 1.25 as (charge for turn around (tx to rx, rx to tx, etc.)) q6 = (0.005a + 0.026a) 30 s = 0.93 as (charge for configuring the atr2406) q7 = (0.005a + 0.026a) 60 s = 1.86 as (charge for settling the loop filter) q8 = (0.005a + 0.057a) 50 s = 3.10 as (charge until valid data can be received) q9 = (0.005a + 0.057a) 210 s = 13.02 as (charge for receiving the packet) q10 = (0.005a + 0.057a) 50 s = 3.1 as (charge for latency before receiving)
21 4779l?ism?09/06 atr2406 a successful packet exchange needs the following charge q = q1 + q2 + q3 + q4 + q5 + q6 + q7 + q8 + q9 + q10 = 192.47 as as the described system is a fhss system with 5 different channels, the system has to do this up to five times before the packet is acknowl edged by the base station. the average will be 2.5 times. in the case of an interfered environment, some more retries may be required; there- fore, it is assumed the factor will be 3. the power-up time is included only once, as the cycle will be completed without po wering up and down the handheld in order to be as power efficient as possible. average current needed for a packet exchange: 155 as + (37.5 as 3) = 267.5 as if the device will be used 1000 times a day 3.1 a average current in active mode: system power down current: current atmega88: 1.25 a current atr2406: 1.0 a current vreg (+ shutdown): 2.75 a assumed average power-down current is 5 a. overall power consumption is 8.1 a it is assumed the system uses a small battery with a capacity of 100 mah. this is 100.000 ah. battery lifetime will be around: 123 45 hours = 514 days = 1.4 years. the most important factor is to get the power-down current as low as possible! example: assume a system where the handheld is used just 10 times per day. i active = 0.031 a and assuming the power-down current of this device is just 4 a. i = 0.031 a + 4 a = 4.03 a battery lifetime will be around 24807 hours = 1033 days = 2.83 years. power-down current is the main factor influencing the battery lifetime.
22 4779l?ism?09/06 atr2406 12. package information 11. ordering information extended type number package remarks moq atr2406-pnqg qfn32 - 5x5 taped and reeled, pb-free 4000 atr2406-dev-board ? rf module 1 atr2406-dev-kit2 ? complete evaluation kit and reference design atr2406 + atmega88 1
23 4779l?ism?09/06 atr2406 13. recommended footprint/landing pattern figure 13-1. recommenced footprint/landing pattern table 13-1. recommended footprint/landing pattern signs sign size a 3.2 mm b 1.2 mm c 0.3 mm a 1.1 mm b 0.3 mm c 0.2 mm d 0.55 mm e 0.5 mm
24 4779l?ism?09/06 atr2406 14. revision history please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. revision no. history 4779l-ism-08/06 ? table ?electrical characteristics? on pages 6 to 8 changed ? section 10 ?appendix: current calculations for a remote control? on pages 20 to 21 changed ? table ?ordering information? on page 22 changed ? minor corrections to grammar and style throughout document 4779k-ism-06/06 ? put datasheet in a new template ? table ?electrical characteristics? on pages 6 to 8 changed ? section 10 ?appendix: current calculations for a remote control? on pages 20 to 21 added ? ordering information on page 22 changed
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